hi,

during conversion of some our products to SiLabs chips I have next question which probably be answered with expert users of this vendor.
The problem is that we need with precission tuning of timings for MOVX instructions which access external data memory (in fact, there is not memory but CPLD fast DMA channel).

Datasheet of C8051F02x says that CIP-51 core executes MOVX for 3 clocks (page 104). Here I think, they mean that it takes 3 clocks + additional selectable stretches if needs.

At same time, looking at page 151 at chapter 16.6 "Timing" I read that

The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing parameters defined by the EMI0TC register.

Then they show an example:

Assuming non-multiplexed operation, the minimum execution time for an off-chip XRAM operation is 5 SYSCLK cycles (1 SYSCLK for /RD or /WR pulse + 4 SYSCLKs).

So I cannot calculate right. The question is: what are these 4 clocks for? As I understand, 3 clocks are paid for instruction fetch (as it said on page 151). But what is about additional one?
For example:
3 clocks = instruction fetch
1 clock = /rd
it gives me 4 clocks. But they said: five.

Could somebody explain, please?

Thanks,
Oleg