The “freeze” disappears if I program the two interrupt with the same priority level (level 0).

That indicates that it's the 'rule':
every priority level must have it's own register bank
that was broken.

If you have interrupts at different priorities using the same bank, the higher priority interrupt, if it occur during the execution of the lower priority, will really screw it up.

Since the compiler does not 'know' the interrupt priorities, it or the linker can not determine that, in the case shown above, even with 'using' specified push and pop would be required.

My 'system' is:
all prt 0 (lowest) interrupts use bank 1
all prt 1 (highest) interrupts use bank 2
on the 4 level derivatives, I use only 3 and the added higher priority get bank 3

and I have no problems.

As to Peters comments "avoid using", sure, you may gain a few DATA slots, but the overhead in the ISR is far bigger. A "modify PSW" is by far faster than pushing and popping.

Erik