But say if we use soft routines for I2C handling with micro being master and some other device say a PCF8574 port expander being slave mode & say I am communicating on soft I2C at 50kHz and while data transfer was on there is an interrupt which lasts for some time say 6mS interrupting I2C data transfer. Upon return from interrupt the micro will again start executing the soft I2C data transfer. In such an event will there be any problem or not? Friends I have never come across any problem due to above stuff so far but was just wondering can such a thing ever lead to problem or I2C bus immune to such timing disturbances.

The IIC bus is theoritically timing insensitive. However, I doubt that IIC chips are tested at 500Hz (~6ms pulse). Somewhere in the old DNA computer there is something about an IIC chip (do not ask which, my memory is not THAT good) that times out to avoid latch-up.

I use the verbage "fix" not "solution" because the solution is to use a chip with hardware IIC such as the P89C66x or P89LPC93x.

1) make the soft IIC timer driven instead of waitloop.
2) make the IIC timer highest priority.

The fact that any IIC operation is (or - at least - should be) very short, the higher priority IIC timer int should not kill anything.

On another note: a 6ms ISR will give you heaps of trouble, not only with IIC.

Erik