the other problem with jtag is that you can get a logic analyser which can read logic state of a fpga through the jtag port but it is expensive and implementing the logic probe in the fpga means that resources are used the logic gets slowed down.
The ideal solution would be to have a generic model of a 8052 and add on modules to model each specific device.That way the customer could buy a generic emulator and a hdl model for the specific processor and the ports would be visible simply and easily.Mind you the manufacturers might not be happy about people having synthesisable hdl for their processors.