for an example of a dual-port memory that doesn't require flags or whatever, just have a look at the 74LS670. It's just nybble-wide, but you get the picture. When you read, you get what's in the memory. If it's being written at the time, you get what's in the memory. If you violate setup and hold times, you still get what's in the memory. Sometimes it's worth the risk, since, sometimes, the risk is small.

If the write window is small, and it's isolated from the read window, it's easy to avoid problems. If your DPM is slow, and your MCU's are fast, then you'll have a greater risk of invalid data than if your DPM is fast and your MCU's are slow. How you design the interface timing will determine the level of risk.

If you have two potentially contending MCU's, one approach might be to limit each MCU's access window to half the available time by limiting each MCU's window to half the counts on a 4-phase clock, with each MCU writing on his first phase and reading on the second. That way he reads what he wrote, if he's writing, but reads what was already there if he's just reading.

It's all in the synchronization logic.

RE