There's really a lot of information that needs to be put on the table before any one can provide a reasonable guess as to what's going on here. We'd need the clock rate, the MCU type, the EEPROM type (some of them have longer write cycles than read cycles) and the speed spec of the 8255, though that's probably not an issue, since it's being manipulated in firmware via ports rather than memory-mapped bus access.

In reality, most "classic" 805x types are slow enough to work with some 8255's. External memory cycle lengths are adequate for 8255 accesses with the 200 ns parts at rates below 24 MHz. All bets are off with the faster parts, particularly those using fewer than the classic 12 ticks per cycle, of course.

From among the parts too fast for the 200 ns 8255, the MAXIM/DALLAS DS89C4x0 parts have a firmware controllable bus cycle lenght that differs between internal and external memory cycles. When you fiddle with the configuration of the memory map, in software, you also get to fiddle with the external bus cycle length, and that's what I figured might help.

It's true that Lattice still offers the older MACHx series devices, of which some are 5-volt compatible. In fact, XILINX (XC9500) and Altera (MAX7000) also offer CPLDs of limited size that are 5-volt compatible as well. They just aren't the latest, greatest, and, for that matter, cheapest devices available. SOmetimes they're pretty cheap on eBay, however.

RE