hi,

First of all, AT89S52 datasheet says:

--------------------------------------------------------------------
After Reset signal is high, SCK should be low for at least 64 system
clocks before it goes high to clock in the enable data bytes.
No pulsing of Reset signal is necessary.
SCK should be no faster than 1/16 of the system clock at XTAL1.
--------------------------------------------------------------------

So after setb RST you need with clr SCK line before delay.

Another issue is that it seems you do not fully understand how SPI link does work. You see, SPI is designed such way that at time you are sending a byte via MOSI pin, you receiving another byte from slave device via MISO pin. As result, your shift routines should be re-wrote into one subroutine which does send and receive bytes simultaneously. What I mean is:

; ...
; Enable writes to code memory.
	mov a, #0ACh	; send first byte of enable code
	call spi_it 	;
	mov a, #053h	; send second byte
	call spi_it 	;
	mov a, #0FFh	; send third byte as dummy
	call spi_it 	;
	mov a, #0FFh	; send fourth byte dummy for receiving 69h
	call spi_it 	;
	cjne A,#069h,enable_error ; received byte is not valid confirm one

; here we are okay to continue
;...
;...

;***************************************************************
spi_it:
; Shift out a byte, most significant bit first.
; Shift in a byte, most significant bit first.
; SCK expected low on entry. Return with SCK low.
; Called with data to send in A.
; Returned with received data byte in A.

	mov r7, #8 	; bit counter
spi_it_loop:
	mov c,MISO 	; input bit
	rlc a 		; move bit into CY
	mov MOSI,c 	; output bit
;
; add delay here with time at least 8 clocks of slave device crystal period
;
	setb SCK 	; raise clock
;
; add delay here with time at least 8 clocks of slave device crystal period
;
	clr SCK 	; drop clock
	djnz r7,spi_it_loop ; next bit
	ret

By the way, another suggestion is to use AT89S53, AT89S8253 etc device with built-in hardware SPI as master device. This way all SPI communication will be done with hardware and you just write or read bytes from SPI Data Register then.

P.S. All the code above is just an type-as-is and not tested.

Regards,
Oleg