| ??? 07/15/05 12:50 Read: times |
#97428 - Re: I2C Interrupts. Responding to: ???'s previous message |
Dear Bernhard,
Is the IRQ asserted at the beginn or at the end of the ACK byte. When is the next I2DAT overwritten/needed? Your LPC will generate I2C interrupt after tha ACK or NACK has been transmitted / received. As the I2DAT has no buffer there is pretty less time to save or load I2DAT after an IRQ. As a slave receiver I asume I have about 10 us before I2DATA is overwritten. But what as a slave transmitter? 5us? The S1DAT has no buffer it is one byte register. But there's absolutely no need to worry about received data in S1DAT overwritten. When some data is recieved in S1DAT through I2C SI flag is set. Untill your software clear the SI flag I2C bus is freezed by your slave LPC stretching the SCL low. Only after you clear SI flag I2C bus SCL line is released so that further I2C transmissions continue. As a slave timming is more critical than as a master, because I have no influence on the clock. I2C supports this for slaves, by clamping SCL down. But I don't know wheter LPC HW supports this. Yes as said earlier LPC hardware will pull the SCL low automatically if an earlier I2C interrupt flag SI is not cleared. Regards, Prahlad Purohit |
| Topic | Author | Date |
| LPC925/935 as I2C slave | 01/01/70 00:00 | |
| Re: I2C | 01/01/70 00:00 | |
| Re: I2C Interrupts. | 01/01/70 00:00 | |
sometimes things can be realized from lo | 01/01/70 00:00 |