Thanks Peter,

My first thought on this problem was the added bus capacitance was causing noise on the _PSEN and ALE lines, but these look OK, and I am using HCMOS logic for all the parts, so I don't believe that it's a glitch here.

App note 57 was interesting because it mentions the Tllpl spec where the hold time for the address latch is too short for clocks greater than 19.23MHz. Im only running as 12.288MHz, but it could be that my bus capacitance is requiring a longer hold time. Ill look into it.

Patrick