As for possible bus contention with previous SRAM read data, the
"SRAM spec indicates the data bus shouldn’t be driven until tOHZ
after the end of a previous read cycle to the same SRAM. Whether
this presents a problem depends on the system configuration.
In this example, the SRAM is being used for data access only
(i.e., connected to RD and WR). Noting that external data cycles are
always separated by an (internal or external) instruction fetch, it is
impossible for back-to-back accesses to occur with a data-only
memory.
Though not a factor in this example, meeting the tOHZ spec could be
of concern in a system that 1) overlaps code and data into a single
64K space (i.e., by ANDing PSEN and RD) and 2) fetches a data
write instruction (ex: MOVX @DPTR,A) from the same SRAM to
which the write is targeted. In this case, the tail end of the opcode
(MOVX) fetch may collide with the beginning of the subsequent
address (DPTR) output if the tOHZ spec isn’t met."