Oleg,

ad 1.: I don't know which kind of the Intel and Atmel manual you have, but as far as I have checked the Atmel and Philips version differs from the presumably original Intel manual only in formatting.
Namely, I see the same note under the Instructions That Affect Flag Settings table in both Intel's Programmer's guide (downloaded as 27238302.pdf page 2-21) and Atmel's 8051 Microcontrollers Hardware Manual (doc4316.pdf, rev.4316C–8051–05/04, page 1-20) (and also in the already mentioned Philips version):

ad 2.: Great point!
It is true indeed that P is within PSW is manipulated in an another way than described within the "bibles" - and that might be perhaps the first defficiency of the "bibles" I have seen so far (and the discussions here in the last months subjected them to real deep scrutiny) - so it might perhaps deserve an another note under the mentioned table.
Nevertheless, for practical reasons, the P flag works the very same way as the non-existent (or non-user-accessible?) Z-flag - it gets updated at the end of each cycle, representing the current status of accumulator (see description of P flag in PSW in the same documents). The only difference to Z flag is, that there is no dedicated conditional branch such as JZ/JNZ; and that it can be used in mov C,P instruction.
Of course, normally one would preserve the accumulator accross interrupts, so the P flag gets naturally "preserved", too - so this "non-conformance" might have consequences only in rather extrenme examples. But it is certainly good to be aware of the existence of it.

This also clearly demonstrates how peculiar the architecture of '51 is and how easily it can confuse even those who already use it for quite a time - especially if those are also involved with different architectures. That's why I tried to start a different approach of describing the '51 architecture from the software point of view in the '51 wiki, stressing these oddities (which are confusing me, too) - sadly, having no feedback nor corrections to it...

Jan Waclawek