This is purely theoretical. I realize the standard 8051 is setup to address 64k through a latch chip, but I was wondering if someone had ever tried to address much, much larger amounts of ram than this with an 8051?

I noticed that some of the 8051's 16-bit math routines are basically "emulated" using two 8-bit registers. Since there are 32 pins for the 4 ports, I was wondering if anyone had tried addressing say, 16mb to 4gb. It seems to me, that it should be possible to address a 16Mb x 8bit group.

Could not it be possible to output 3 ports for addressing, and one port for data?

It seems to me it would be fairly simply to make a counter using three registers, one for each port, that would count up, and carry over to the more significant 8 bit register. A simple loop then, could "in theory" be made to count up and cycle through the addresses, up to 3 ports worth, or around 16Mb.

Keep in mind :
1. I'm not talking practicality. This is hypothetical. There are obviously much better solutions for addressing this large amount of ram.
2. Byte wide data.
3. I realize this would be somewhat (understatement?) overwhelming for an 8051, and that reading this data and then processing it would probably be pointless anyway. Also, probably, other than addressing in a counting fashion, the code for addressing at seamingly "random" points would be... difficult to manage.
4. Specifically, I was thinking of a digital recording system that could take advantage of old memory modules from computers. An ADC and a DAC, cycling through the memory could record a significant amount of sound, digitally. If counting up from 0, and assuming the sampling rate to be around 10Khz, 16Mb would last around 28 minutes.

This is more of a "could it be done / has anyone done it" type of situation. And we're not even talking about the refresh circuitry required for DRAM...

Any thoughts?