??? 11/08/05 21:03 Read: times |
#103440 - sorry, here is the loop and the ISR Responding to: ???'s previous message |
x,y,sadch,sadcon are all UCHAR
s[] is an XDATA UCHAR array Here is main loop: for (y = 0; y < 224; y += 4) { ADCON = 8; s[28+y] = TH0; s[29+y] = TL0; s[30+y] = sadch >> 6; s[31+y] = (sadch << 2) | (sadcon >> 6); sadch = ADCH; sadcon = ADCON; } Here is the ISR: void adc_intr() interrupt 10 _naked using 0 { _asm push acc _endasm; ADCON &= 0xc0; _asm pop acc _endasm; } What the main loop does is build the payload of a UDP packet that will later be sent to the host over a UDP/IP/SLIP interface. It sends the 16 bit timer value of timer 0 as well as the 10 bit ADC result as a 16 bit value. I am using SDCC 2.4.0. The code it generates works fine, it's just that there is tremendous optimization I can do by hand. But that's not my problem. It looks as if the conversion is being done in serial with the loop code. I would have liked for the 50 cycle conversion to be done sometime near the end of the loop, so that when the loop begins again, there is an ADC result ready for it to process. |
Topic | Author | Date |
Timing of A/D conversion on 80c552 | 01/01/70 00:00 | |
show your code | 01/01/70 00:00 | |
sorry, here is the loop and the ISR | 01/01/70 00:00 | |
I see no such thing, please cut and past | 01/01/70 00:00 | |
you're right. I took out the setting of | 01/01/70 00:00 | |
PLEASE cut and paste, as is it will not | 01/01/70 00:00 | |
OK, nevermind. The whole code is way too | 01/01/70 00:00 | |
often the reason for an unexplainable pr | 01/01/70 00:00 | |
Funny you mention that![]() | 01/01/70 00:00 | |
inconsistent | 01/01/70 00:00 | |
since wwe all know that you get what you | 01/01/70 00:00 | |
True. I fully expect to have to study | 01/01/70 00:00 |