| ??? 11/09/05 15:33 Read: times |
#103487 - Funny you mention that Responding to: ???'s previous message |
In my interrupt handler for the ADC, I didn't have a RETI. Having declared it using the _naked keyword, the compiler relied on my _asm in its entirety. Fortunately, the timer 0 ISR was in memory right after the ADC ISR. So it was eventually getting a RETI instruction, after several useless PUSH and POP instructions.
I have since dropped the use of the ADC interrupt. I now rely solely on clock cycle timing to know when the ADC is ready and have the loop down to 54 cycles total, or 34,133 per second. Which includes writing the results and timestamps to sequential XDATA locations. |
| Topic | Author | Date |
| Timing of A/D conversion on 80c552 | 01/01/70 00:00 | |
| show your code | 01/01/70 00:00 | |
| sorry, here is the loop and the ISR | 01/01/70 00:00 | |
| I see no such thing, please cut and past | 01/01/70 00:00 | |
| you're right. I took out the setting of | 01/01/70 00:00 | |
| PLEASE cut and paste, as is it will not | 01/01/70 00:00 | |
| OK, nevermind. The whole code is way too | 01/01/70 00:00 | |
| often the reason for an unexplainable pr | 01/01/70 00:00 | |
Funny you mention that | 01/01/70 00:00 | |
| inconsistent | 01/01/70 00:00 | |
| since wwe all know that you get what you | 01/01/70 00:00 | |
| True. I fully expect to have to study | 01/01/70 00:00 |