From the forthcoming rev. M errata sheet:

1. During SPI communications, when the SPI is disabled by clearing the SPE (SPCR.6) bit, the interface is only reset for one clock cycle afterwards. This will result in clock glitches or missing clocks if the user is trying to switch the clock modes (CPOL, CPHA) even if SPE is 0.
The work-around in software is to make sure that the SPE bit toggles 1-->0 after the mode bits have changed:

Assembly:

Ex: Change CPHA when SPI is still enabled (SPE=1):
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; SPCR was 50h
MOV SPCR, #014h ; clear SPE and set CPHA
ORL SPCR, #040h ; set SPE

Ex: Change CPHA when SPI is not enabled (SPE=0):
--------------------------------
; SPCR was 10h
MOV SPCR, #054h ; set SPE and set CPHA
ANL SPCR, #0BFh ; clear SPE
ORL SPCR, #040h ; set SPE

C language:

Ex: Change CPHA when SPI is still enabled (SPE=1):
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/* SPCR was 0x50 */
SPCR = 0x14; /* clear SPE and set CPHA */
SPCR = SPCR | 0x40; /* set SPE */

Ex: Change CPHA when SPI is not enabled (SPE=0):
--------------------------------
/* SPCR was 0x10 */
SPCR = 0x54 /* set SPE and set CPHA */
SPCR = SPCR & 0xBF /* clear SPE */
SPCR = SPCR | 0x40 /* set SPE */


2. Timer 1 does not work as a baud rate generator in Modes 0 or 1. This is for very low baud rates (one customer used 5 bps). Most customers use Mode 2, which works fine.
Some AT89S8253 customers may be able to use Timer 2 for slow baud rates, although Timer 2 cannot go quite as low as Timer 1 because Timer 2 is 12 times faster than Timer 1 in baud generator mode.

GB