Mohit,
Sorry for the confusion..I tried to simplify things and my answer ended up incomplete. So here are the full details.
My product has CPU, PLDs', EPROM, RTC, RAM, (all CMOS) etc, and I needed to only back up the RAM, power the RTC. No other devices were to be supplied.
The final circuit I arrived at was as follows.
1) Tracing from VCC, through Rcharge (as in my first reply) in parallel with a Shottky (D1 - cathode to VCC) to Batt pos.
2) from Batt neg, through another Shottky (D2) to GND (cathode to GND).
3) RAM & RTC sit between VCC and Batt neg. All other devices sit between VCC and GND.
When you trace out this circuit, you will see that only the devices between VCC and Batt neg are supplied by the battery, D2 isolating the others from Batt neg.
Shottkys are used because of their low Vf.
Explanation of D1:
I found that as VCC decayed to Vbatt, there was a point where the EPROM and PLDs' momentarily pulled significant current (probably due to undervoltage operation - the path for this current is pretty obscure) from the battery such that a significant voltage drop occurs across Rcharge, thus further reducing the supply to these devices and leading to a latchup condition in the EPROM (27C128) and PLDs' that drained the battery very quickly.

D1 limits the voltage drop across Rcharge to Vf during the transition from VCC to Vbatt. It entirely eliminated the latchup described above.

Hope this helps

regards,
Allan