Hi,

several postings again about Data corruption on NVRAM / EEPROM.

In such cases a supervisor chip must be used !
This chip must generate proper reset for the CPU and disable the CS signal from the NVRAM / EEPROM during low power. Also if battery powered SRAM was used it must switch the VCC voltage without any glitch.

Additional a good pcb with big and short ground and VCC connections was needed.

Data corruption on NVRAM / EEPROM can be initiated with any short WR pulse.

So better data security can always be reached with serial EEPROM (e.g. AT24C512) or EEPROM / Flash with software data protection (e.g. AT29C512). Then a single pulse can not initiate wrong write cycles. Always a long sequence of defined data and address cycles or a longs serial bit stream enable the write cycle.
With such devices I detect never any data loss.
Nevertheless I use supervisor circuits to generate always a proper reset to the micro.


Peter