some comments to Peters postion:

"In such cases a supervisor chip must be used !"
And In most other cases, I have come to the conclusion that unless you are using OTP, the supervisor chip is mandatory.

"This chip must generate proper reset for the CPU and disable the CS signal from the NVRAM / EEPROM during low power."
As most memories are !CS this is automatic as the uC reset port pins high.

" Also if battery powered SRAM was used it must switch the VCC voltage without any glitch."
Holding !CS high will do it.

"Additional a good pcb with big and short ground and VCC connections was needed."
You just earned the good housekeeping seal.

"Data corruption on NVRAM / EEPROM can be initiated with any short WR pulse."
I have used battery backed NV RAM for ages and never lost a byte.

One item Peter forgot is to be very liberal with decoupling capacitors, I will rather lose a penny for a capacitor than a program blown every blue moon. I have no proof of the importance of decoupling capacitors on each and every chip mounted very close to the Vcc and gnd pins. I have had to fight all kinds of problems in designs without and never in designs with. It is, of course, possible that chip xyz will work fine without the decoupler, but I have no means of knowing which will and which wo'nt and no guide is available to my knowledge. A cap within 5mm of every VCC and a tantalum in parrallel at uC and memory is my rule. One case tha I know creates a major spike is setting a port pin that is held low high to use as input, just look at the little schematic of the port in the data sheet.

"With such devices I detect never any data loss."
Following the above rules, I have not lost any data from battery backed RAM either.

Erik