OK, I get it but I am using a 4 input and get to get my CS for my existing Ram each input represents 8K of address space, it is just the way I was taught I guess, how would I implement a latch this way? as I said the lower 32k is ram the upper 32k is decoded for RAM I am using 138 latches, so the first 4 decoded pins run to the AND gate to select my RAM...So I am still unclear as to how I could latch the CS line from one RAM bank to another.....