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???
06/13/06 04:13
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#118188 - This may be one reason
Responding to: ???'s previous message
Erik Malund said:

Before turning the bus on last interrupt you have to wait 1/2 (I wait one full) bit time because the interrupt happens NOT at the end of the stop bit but in the middle.

Turning the bus immediately on the interrupt could very well show what you see.

Erik


I am turning off TX enable as soon as TI interrupt occurs.
This is one point to check. Shall check and revert

KG


List of 14 messages in thread
TopicAuthorDate
Bad MAX 485 IC ?            01/01/70 00:00      
   Voltage between Earth and Neutral..            01/01/70 00:00      
      also            01/01/70 00:00      
         This may be one reason            01/01/70 00:00      
   What's a DB9?            01/01/70 00:00      
      Correction . DE9 - not DB9            01/01/70 00:00      
         Earthed Shell to the shield of cable            01/01/70 00:00      
   Mild shocks...            01/01/70 00:00      
      E1 is a pump controller            01/01/70 00:00      
         Open "E1" and have a look at            01/01/70 00:00      
      you missed one            01/01/70 00:00      
         Only one reciever            01/01/70 00:00      
            Yes. Only one receiver            01/01/70 00:00      
               all uC developers should be Boy Scouts            01/01/70 00:00      

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