| ??? 08/10/06 02:23 Read: times |
#121943 - usermanual of 89LPC9xx insufficient Responding to: ???'s previous message |
Erik Malund said:
Mode 2 has to be used.
that will not do it as I did show in my post, it will at best produce 1/2 the frequency the Op wants. However had the OP done the horrendous, awful, terrible, cumbersome effort of looking in the user manual, he would have found: "CLKOUT CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the real time clock/system timer." Erik I have checked the value of UCFG1 through my parallel programmer (All-100). It is using internal RC osc as clock source. Actually, I could generate a pulse with 3.xxMHz frequency to port 3.0 (XTAL2) after i have enabled ENCLK - TRIM.6. However, my hardware grayscale clock is connected to P0.5. Thus, I am thinking of using timer 0 mode 1 (16-bit timer) to generate a clock pulse with frequency (3.xxMHz/2). Refering to 89LPC9xx usermanual, the clock used for timer is PCLK which is 7.xxMhz/2 (CCLK/2). Hence, i thought the timer reload value should be calculated this way: (65535-x)(1/3.xxM) = 1/3.xxM => x = 65534 => TH0 = 0xff, TL0 = 0xfe I think the above formula is incorrect since the output doesn't create a clock pulse of 3.xxMhz/2. I am not quite familiar with LPC9xx series, but for 80c51 series, the calculation is (65535-x)(12/fOSC) = 1/fTimer And the usermanual doesn't mention much about the formula to calculate it... Anyone has any idea to calculate it? My timer routine is as follows: TMR0_ISR: CPL P0.5 CLR TF0 MOV TH0,#0FFH MOV TL0,#0FEH RETI Regards, IVan |
