I have a few questions regarding tmr/ctr mode 3.

1. According to the "the bible", when tmr/ctr0 is in mode 3, TH0 "takes over" the use of TR1 and TF1 from tmr/ctr1. Does this also mean that TR1 no longer controls operation of tmr/ctr1?

2. When tmr/ctr0 is in mode 3, do GATE1 and INT1 still control operation of tmr/ctr1? The DS5000 User's Guide states that GATE1 is unused (which I assume means INT1 is unused), but it's not quite as clear in the bible.

3. When tmr/ctr0 is in mode 3, does the C/T bit still control operation of tmr/ctr1? The DS5000 User's Guide states that tmr/ctr1 is forced to operate as a timer when tmr/ctr0 is in mode 3. The bible states that TH0 is locked into a timer function, but doesn't mention whether or not that is the case for tmr/ctr1.

I believe the answers are yes, no, no, but just wanted to confirm my suspicions. (The tutorial section also seems to suggest that when tmr/ctr0 is in mode 0 that none of the control inputs to tmr/ctr1 have an effect, and it is locked into a timer function.)

What would really be helpful is an additional set of block diagrams which shows tmr/ctr1 in modes 0-2 when tmr/ctr0 is in mode 3. If I'm correct, the drawings would look like figures 7 and 9 in the bible, but with the front-end logic removed, and the OSC/12 input fed direcly into the count register (no control logic, and no C/T switch).

Thanks in advance for your help ...

Scott Gurst
Electrical Engineer
Laboratory for Atmospheric and Space Physics
1234 Innovation Drive
Boulder, CO 80303