??? 08/29/06 17:30 Modified: 08/29/06 17:39 Read: times |
#123347 - mode 3 Responding to: ???'s previous message |
"makes half of t0 t1. thus 2 8 bit counters"
This allow 2 8 bit counters together with t1 as a baudrate generator. if you are running out of timer/counters and this does not solve your problem, look into either a derivative with a PCA or CGA or, maybe better, there are derivatives with (more than?) 4 timers such as many SILabs derivatives. as an example, here it is for the SILabs f12x which does not fully agree with what you have. What derivative do you use? "In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 interrupt. Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0, 1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However, the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode settings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1, configure it for Mode 3" Erik |
Topic | Author | Date |
Timer/Counter Mode 3 | 01/01/70 00:00 | |
mode 3 | 01/01/70 00:00 | |
Looks like DS5000 | 01/01/70 00:00 | |
Oregano Core | 01/01/70 00:00 | |
I suspect that this 'unorthodox' mode that I have | 01/01/70 00:00 | |
Timer mode 3![]() | 01/01/70 00:00 |