??? 09/06/06 17:56 Read: times |
#123773 - IOW\ and IOR\ Responding to: ???'s previous message |
This signal nomenclature is a vestige of old x86 designs. Those processors have two "spaces," a memory space and an I/O space. (One limitation was that the I/O space address bus was 16 bits wide, and on the original IBM PC, only the lower 10 bits were decoded for ISA bus access!)
The idea was that you could put I/O devices in the I/O space and just memory in the memory space. Of course now we just use memory-mapped I/O because the memory spaces (4 GB for 32-bit address bus and a zillion bytes for 64-bit buses) are so large. So, anyways, that UART was designed for easy connection to an x86-type bus, hence the pin names. But all you really need to understand is that IOR\ is the read strobe and IOW\ is the write strobe. I don't remember if that UART also had a chip-select input. I imagine that it does, so you'll have to decode addresses to drive the chip select and simply connect the micro's RD\ output to IOR\ and the WR\ output to IOW\. If the chip select doesn't exist, you'll have to decode the address and gate RD\ and WR\ with the decode result to drive IOR\ and IOW\. -a |
Topic | Author | Date |
/R & /W OR /IOR & /IOW | 01/01/70 00:00 | |
Oops | 01/01/70 00:00 | |
Make preview compulsory? | 01/01/70 00:00 | |
IIRC | 01/01/70 00:00 | |
Thanx Neil | 01/01/70 00:00 | |
Reading time | 01/01/70 00:00 | |
IOW\ and IOR\ | 01/01/70 00:00 | |
Spaces... | 01/01/70 00:00 | |
It has a few more ... and what\'s with the \\? | 01/01/70 00:00 | |
Too many Andies... | 01/01/70 00:00 | |
As Sun Ra said, | 01/01/70 00:00 | |
and I thought I was the only one | 01/01/70 00:00 | |
Whats this | 01/01/70 00:00 | |
need to be specific | 01/01/70 00:00 | |
Improper? | 01/01/70 00:00 | |
go back and read ... | 01/01/70 00:00 | |
and also read... | 01/01/70 00:00 | |
What I understood ? | 01/01/70 00:00 | |
No. | 01/01/70 00:00 | |
You mean Yes?! | 01/01/70 00:00 | |
which is why | 01/01/70 00:00 | |
THANKX everybody![]() | 01/01/70 00:00 |