Let's assume you have the following contents of external code ROM:
0000 74 15 - mov a,#15h
0002 F5 90 - mov p1,a;
The following happens (not exactly, but for the purpose of ur explanation this suffices):
- 00 (low part of program counter PC) gets issued on P0 pins, 00 (high part of PC) on P2 pins, ALE pulses high and low (so that the low address from P0 can be latched)
- P0 floats, /PSEN is pulsed low so that the ROM puts the data from address 0000 (=74) onto its data bus = P0 from where the '51 latches it into its internal instruction latch.
- '51 decodes the instruction and finds out that it needs one more byte. Meantime, PC is incremented.
- 01 (PC low) onto P0, 00 (PC high) onto P2, ALE pulsed high
- P0 floats, /PSEN pulsed low, the byte from ROM (=15) latched in
- '51 further decodes the instruction, finds out that it needs to move the second latched byte into accumulator and so it does. As this instruction is done, '51 knows that the following code memory fetch is the first byte of instruction again. Meantime, PC is incremented.
- 02 (PC low) onto P0, 00 (PC high) onto P2, ALE pulsed high
- P0 floats, /PSEN pulsed low, the byte from ROM (=F5) latched in
- '51 decodes the instruction and finds out that it needs one more byte. Meantime, PC is incremented.
- 03 (PC low) onto P0, 00 (PC high) onto P2, ALE pulsed high
- P0 floats, /PSEN pulsed low, the byte from ROM (=90) latched in
- '51 further decodes the instruction, finds out that it needs to move the contents of accumulator to a directly addressed location with address given by the second byte, which is an address of a SFR (P1); writing to it changes the state of the P1 port pins.
Is it clearer now?
JW