| ??? 07/06/07 08:17 Read: times |
#141543 - Interrupt Latency + Vectoring + Service Responding to: ???'s previous message |
Sorry my incorrect use of words. The cpu will have latency to respond, then vector to the required address in the vector table. This is generally just an LJMP to the actual ISR (interrupt service routine).
And Yes, the ISR will fit into the vector table being 2 bytes long. This would avoid a compiler generated LJMP to a C ISR. This has intrigued me. I am too idle to unpack an oscilloscope but will just use do a frequency count (with an AVR) to see if my suggestion actually works !! The OP wanted a 100kHz signal. He did not specify that it does not jitter. IMHO you need a 8051 variant that can output a PWM signal. Jan Waclawek said:
David Prentice said:
You only have 5 machine cycles to play with anyway including the interrupt vectoring which is between 3 and 8 machine cycles. Just some hairsplitting: the interrupt vectoring is a pretty standard lcall (just generated by hardware), so it takes 2 cycles. What you are talking about is the interrupt latency. In other words, the execution of an interrupt consisting of one bit toggle and reti (i.e. it has to be placed at the 03-0B-13-etc. address) takes 5 cycles, but the toggle might come 3 to 8 cycles after the timer rollover. Now I would need to think hard which one of these two does matter in this particular case, but it's quite late here... :-) JW PS. ... and the jitter will be horrible... |
| Topic | Author | Date |
| How to generate 100 Khz square wave 80C51 | 01/01/70 00:00 | |
| Tips | 01/01/70 00:00 | |
| 1 KHz | 01/01/70 00:00 | |
| that's ... | 01/01/70 00:00 | |
| SI Units | 01/01/70 00:00 | |
| 1024 = Ki | 01/01/70 00:00 | |
| C interrupt overhead | 01/01/70 00:00 | |
| RE: C interrupt overhead | 01/01/70 00:00 | |
| and listen to the guru! :-) | 01/01/70 00:00 | |
| several reasons | 01/01/70 00:00 | |
| Yet another reason to avoid using HLL's! | 01/01/70 00:00 | |
| Optimizations | 01/01/70 00:00 | |
| Use Timer0 auo reload | 01/01/70 00:00 | |
| using | 01/01/70 00:00 | |
| interrupt vectoring vs. latency | 01/01/70 00:00 | |
| Then the Interupt must be in ASM | 01/01/70 00:00 | |
| do you mean... | 01/01/70 00:00 | |
| No | 01/01/70 00:00 | |
| Compiler generated IRQ vectors | 01/01/70 00:00 | |
| OOPS we both meant LJMP REALisr | 01/01/70 00:00 | |
| the original problem... | 01/01/70 00:00 | |
| Interrupt Latency + Vectoring + Service | 01/01/70 00:00 | |
| indufficient info | 01/01/70 00:00 | |
use MCS52 better option | 01/01/70 00:00 |