So if power fails during erase of page 0, you might find that any of the bits that were zero previously, may or not be erased to ones. In fact, bits can become "half erased" and return different values at different times, depending on environmental factors (like temperature).
I did not consider, I was under the impression that flash erase was something like get the power booster running and WHAM!

What would you say if someone came to this forum and said: "I am going to rely on the undefined properties of a device because I think I can't afford one extra LJMP in an ISR".

I don't like to put words in your mouth, but from what I have seen, I expect you would say:

(a) Don't ever base your design on undefined properties of a device, and
(b) If you are so close to the line that you can't afford one extra LJMP somewhere, then use a faster device.
you 'quote' me pretty well;
re a) see above.
re b) the problem is that I'm using the fsatest devuice available. And due to a rton of inherited assembler code an architecture switch is very undesirable.

I will definitely check Jans idea (I like it) and the implication in the 'program itself' device is none (It has no 'fast' ISRs). I was thinking of the devices down the line that will be 'externally' programmed. Here I'm 'caught' in the fact that I use JTAG devices, had they been serial ISP I'd be home. Alas no 100MIPS serial ISP devices exist to my knowledge.

Erik