| ??? 08/02/07 13:58 Read: times |
#142655 - the penalty of an extra ljmp... Responding to: ???'s previous message |
... is so small even in the case of cache miss in the 100MHz SiLabs' you are presumably about to use, that if the associated ISR is likely to grow to a kB and more, this penalty will be almost certainly negligible.
On the other hand, the really fast ISRs, which really need to be squeezed to the last tick, are short, so you can safely assign a relatively small chunk of "reserve" to them. In the SiLabs', you can also play with the jump cache so that the time-critical jumps will be always cached hence executed quickly. JW |
| Topic | Author | Date |
| an attempt at a failsave bootloader | 01/01/70 00:00 | |
| do you REALLY need that 1kB? | 01/01/70 00:00 | |
| I'll have to think on that one - excellent idea | 01/01/70 00:00 | |
| Flash uncertainty | 01/01/70 00:00 | |
| I did not consider | 01/01/70 00:00 | |
| extra jump and enough power | 01/01/70 00:00 | |
| extra junp | 01/01/70 00:00 | |
| no magic idea... | 01/01/70 00:00 | |
| maths problem | 01/01/70 00:00 | |
| I am absolutely sure... | 01/01/70 00:00 | |
| the penalty of an extra ljmp... | 01/01/70 00:00 | |
| Dont ReWrite Page 0 | 01/01/70 00:00 | |
not a PC ... | 01/01/70 00:00 |