| ??? 08/21/07 13:04 Read: times |
#143453 - re Dereks suggestion 'Use a semi system' Responding to: ???'s previous message |
if you do that TAKE CARE.
more than one, doing so, has had the pesky 'once a month bug'. Just visulaize if both processors test !busy at the same time. while the busy check is a valid approach, you need a more elaborate scheme. one that works is a 'master' (M) and a 'master of masters' (MM) scheme. use two wires Mbusy and MMbusy if MM want the SRAM it will check Mbusy and wait till it goes away, then set MMbusy and do its thing if M want the SRAM it will check MMbusy and wait till it goes away. then it will set Mbusy and THEN check MMbusy, and if acive remove Mbusy and wait again, if the second test for MMbusy is 'no' it will do its thing. Erik |
| Topic | Author | Date |
| I2C communication between one 24c02 and two 8051uC | 01/01/70 00:00 | |
| what search? | 01/01/70 00:00 | |
| Search for | 01/01/70 00:00 | |
| if the OP would know the magic keyword... | 01/01/70 00:00 | |
| Oops - missed the two 8051s! | 01/01/70 00:00 | |
| I2C MultiMaster | 01/01/70 00:00 | |
| Do both 8051s need to be masters? | 01/01/70 00:00 | |
| Yes, I want both to be masters | 01/01/70 00:00 | |
| Oscilloscope? | 01/01/70 00:00 | |
| Re | 01/01/70 00:00 | |
| Not quite true | 01/01/70 00:00 | |
| Use a semi system | 01/01/70 00:00 | |
| re Dereks suggestion 'Use a semi system' | 01/01/70 00:00 | |
| Read the I2C Spec Carefully | 01/01/70 00:00 | |
| two uC are able to read .. | 01/01/70 00:00 | |
| Software or Hardware I2C | 01/01/70 00:00 | |
its a software I2C | 01/01/70 00:00 |