Hi Roy,

This is an extract from 80C51 family hardware description, Philips data book famhdwr.pdf

Hope it will help you.

Single-Step Operation

The 80C51 interrupt structure allows single-step execution with very
little software overhead. As previously noted, an interrupt request
will not be responded to while an interrupt of equal priority level is
still in progress, nor will it be responded to after RETI until at least
one other instruction has been executed. Thus, once an interrupt
routine has been entered, it cannot be re-entered until at least one
instruction of the interrupted program is executed. One way to use
this feature for single-step operation is to program one of the
external interrupts (e.g., INT0) to be level-activated. The service
routine for the interrupt will terminate with the following code:

JNB P3.2,$ ;Wait Till INT0 Goes High
JB P3.2,$ ;Wait Till INT0 Goes Low
RETI ;Go Back and Execute One Instruction

Now if the INT0 pin, which is also the P3.2 pin, is held normally low,
the CPU will go right into the External Interrupt 0 routine and stay
there until INT0 is pulsed (from low to high to low). Then it will
execute RETI, go back to the task program, execute one instruction,
and immediately re-enter the External Interrupt 0 routine to await the
next pulsing of P3.2. One step of the task program is executed each
time P3.2 is pulsed.

Best regards,
Silviu