Guys,

If i decifer the debate correctly Kalpak is correct. How about checking with the chip if you want an authorative source. You can expect:

STD 8051: If you address external mem map (XRAM) with @R0 and @R1 then the address (contents of R0/R1) is put out P0 to be latched by ALE and then the data value is either output (qualified by /WR) or read (qualified by /RD). P2 is not disturbed.

If you use @DTPR then P2 outputs the contents of DPH during the time P0 is outputing DPL to be latched by ALE and during the P0 data transfer.

If you do not use @r0,@r1,@dptr, you can use P0, P2 as ports, be sure to use pull-ups on P0 or it just might float "linear" and warm up things.

regards,
p