| ??? 05/18/08 21:30 Read: times |
#154868 - why 5) Responding to: ???'s previous message |
5.> Just for debugging purpose try to read data from master 1 only (let master 2 be idle with SCL & SDA initialised at logic 1).
why 5) this is the ESSENTIAL test, I would go one step further and say let master 2 be removed from the circuit. There is one more thing of concern: are the pins on the 2 uCs open collector (not quasi-bidirectional) as e.g p0 in "the traditional" and dedicated pins in some modern derivatives. The "brief hard pullup" at p1-p3 can wreck havoc on an IIC bus. One question to the OP are you trying to do this without a scope/logic ananlyzer? Erik |
| Topic | Author | Date |
| about I2C and 8051 | 01/01/70 00:00 | |
| Serial EEPROM Issues.... | 01/01/70 00:00 | |
| Insufficient information | 01/01/70 00:00 | |
| check the bus status | 01/01/70 00:00 | |
| Please verify folowing things | 01/01/70 00:00 | |
why 5) | 01/01/70 00:00 |