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10/14/01 06:00
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#15660 - RE: interfacing 93C46 with 89C51
OK, I got it.

What you send it's the output results of C compiler.
This is the main reason for which looks so weird.
Very tight code and small resources : only DPTR, B reg and first register bank.
R0 - 8 bits data to be send or received
R1 - 8 bits MSB for 16 bits data to be send or received (if ORG = "1" logic)
R2 - 7 bits EEPROM address
R3 - the following up to 11 address bits for 93C86 (not used in program)
B register - counter loop for how many bits to be send / received to / from EEPROM; counter loop for write delay
DPTR - the stream of bits to be send to EEPROM including START bit, two opcode, 7 bits address and 8/16 data bits

When the internal RAM location 60 is displayed you should see something different from 01H.
What you see ?
The write delay is made up of 220 ticks, (the 0x8179 location value) where one tick is the period during execution of DJNZ instruction, multiplied by 22 (the 0x817E location value). The total period should exceed 10ms to be absolute sure. Check this value which depends on crystal clock period and number of clock / machine cycle.
At the end of "status routine" the Carry flag is set if we didn't received the ready signal from EEPROM after write delay. I don't see in program any care about this flag. You can check, too.

For this I'm not sure, maybe someone 8052 guru to corect me :
In the read procedure we should have nine rising edge of signal applied on the S input. First for dummy '0' bit, the next eight for byte data. In the "shin procedure" loop we have only 8 SETB - CLR pairs; the B reg loaded with 08H (81A8 location).

Even if it's not working OK now, for the future it's wise to end every write cycle with EWDS instruction :
ewds:
SETB 92H
MOV DPTR,#0200H
MOV 0F0H,#0AH
LCALL 81B7H(OUTDATA)
CLR 92H
RET

More than that it's mandatory to erase the byte before writing :
erase:
SETB 92H
MOV DPL,#07H
MOV 0F0H,#03H
LCALL 81B7H(outdata)
MOV DPL,R2
MOV DPH,R3
MOV 0F0H,#07H
LCALL 81B7H(outdata)
CLR 92H
LCALL 8171H(status)

For the people that like to help HEMANTH I can post the source with all variables replaced, in order to be easy readable. Only if requested, since it's no wise to load the space forum.

Best regards,
Silviu
RET

List of 7 messages in thread
TopicAuthorDate
interfacing 93C46 with 89C51            01/01/70 00:00      
RE: interfacing 93C46 with 89C51            01/01/70 00:00      
RE: interfacing 93C46 with 89C51            01/01/70 00:00      
RE: interfacing 93C46 with 89C51            01/01/70 00:00      
RE: interfacing 93C46 with 89C51            01/01/70 00:00      
RE: interfacing 93C46 with 89C51            01/01/70 00:00      
RE: interfacing 93C46 with 89C51            01/01/70 00:00      

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