It means that after some 100K of a mix of write and erase cycles to specific locations that the memory cells will be substantially degraded in terms of performance and functionality. The degradation could mean these types of things....

1) It may require a longer time to erase a memory cell from "0" back to "1".

2) It may no no longer be possible to restore a cell back to "1" at all.

3) It may require a longer time to write a memory cell from "1" to a programmed bit level of "0".

4) It may no no longer be possible to write a cell to "0" at all.

5) When programming with nominal timing the part may not be able to retain the programmed memory content for the specified retention period.

6) Depending upon the internal device circuit design the read back access time to valid read data may extend beyond the specified read access time.

It is important to note that the 100K number is not a brick wall that once reached renders the part instantly bad and/or reduced performance. More to the point the 100K number represents the number of cycles after which a statistical number of devices will begin to show reduced performance or loss of functionality. Some devices may actually show reduced performance before the 100K erase/write cycles have occurred.

Also note that, depending on the device geometry and internal circuit design the endurance cycles accumulate for the memory bytes, blocks or pages that are actually erased or re-programmed. Other blocks that are not used or accessed in any way will not accumulate counts of endurance cycles against themselves.

Michael Karas