Here I have built up a simulation of a typical 5V to 3V level translator circuit using NPN transistors that is typical of what you may see in many schematics:


Now here you may see the resulting response of such circuit. Note in particular the long delays seen on the edges related to state transitions where a transistor is turning off.


The delays seen in even this typical circuit are on the order of 2 to 2.5 microseconds. If the bit bang timing being generated happened to depend on signals that were changing at at the same time on the MCU side the delay could easily destroy a setup or hold time at the target side. This needs to be taken into account in the whole implementation strategy.

2.5 microseconds may not sound like much but when you have an interface that wants to clock at say 100kHz this delay ends up being equivalent to 25% if the clock period!!

Michael Karas