Hi,

I'm trying to create an 8052 program that will copy the contents of the prom
(flash) into ram, then switch to running the code in ram. There is hardware provision to 'swap' what appears (to the uC) as XDATA to CODE and vice-versa.
(This is done via gating of the PSEN and RD lines). The swap is performed via setting an output pin to 0.

The code appears to run OK, copying an exact image of the flash to ram (inc. int vectors, etc), so the two code images share the same address locations, but different devices. The problem occurs when the switch is made, when the 8052 watchdog causes a reset.

Can anyone suggest why this might be happening? I was wondering about assertion times of the output pin during the fetch cycle, but since both flash and ram are identical, would this be a problem?

Any help most appreciated!

David.