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11/23/01 18:16
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 		 #16870 - RE: Clarification.
I would do this with an FPGA, or a big CPLD.


List of 6 messages in thread
TopicAuthorDate
T1 to T1 Time slot interchange.            01/01/70 00:00      
Clarification.            01/01/70 00:00      
RE: T1 to T1 Time slot interchange.            01/01/70 00:00      
RE: Clarification.            01/01/70 00:00      
RE: Clarification.            01/01/70 00:00      
Thanks            01/01/70 00:00      

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