I would expect exactly this behaviour only if all of the instructions at the jump target would be single-world single-cycle (NOP-like). As most of the instructions (even the single-word) take more than that, I would expect slightly less penalty in average.
the length of the first instruction doe not matter, the next one needs to be cached.

So, in effect, that all means, that a jump to a non-cached position may result in delay of 4-7 cycles (the 1-3 extra cycles would "happen" at a different instruction and under the circumstances outlined above, but I think it is an adequate description for the purpose of a worst-case description for the table). A jump into a non-cached position may result in delay of 1-3 cycles, if the next word is not cached yet. Correct?
if the next instruction is cache-locked, there may be a delay, see above

Erik