| ??? 12/15/11 23:01 Read: times |
#185111 - no cache for 50MHz Responding to: ???'s previous message |
Jan Waclawek said:
I am also curious [...] how does this mechanism work with the 50MHz-ers. Most (if not all) 50 MHz limited device families (e.g. C8051F340) do not have a cache. They only have a prefetch engine. |
| Topic | Author | Date |
| '51 derivatives cycle comparison table updated | 01/01/70 00:00 | |
| above about 40 Mhz devices may need extra cycles | 01/01/70 00:00 | |
| silabs with cache | 01/01/70 00:00 | |
| Ok, a SILabs cache lesson | 01/01/70 00:00 | |
| Bytes | 01/01/70 00:00 | |
| ecc? | 01/01/70 00:00 | |
| not the cookies | 01/01/70 00:00 | |
| Washed? | 01/01/70 00:00 | |
| am I as has happened before ... | 01/01/70 00:00 | |
| Is that how it's spelled? | 01/01/70 00:00 | |
| re: Washed? | 01/01/70 00:00 | |
| jump cache miss penalty | 01/01/70 00:00 | |
| clarifications | 01/01/70 00:00 | |
| no cache for 50MHz | 01/01/70 00:00 | |
| surely not all | 01/01/70 00:00 | |
| you missed a word | 01/01/70 00:00 | |
| more update | 01/01/70 00:00 | |
| Table suggestions | 01/01/70 00:00 | |
Updated MC51 supports Cycle Define | 01/01/70 00:00 |