This is an old "semantic" argument which is (unlike most semantic based issues) absolutely valid. 16 bit Code Model vs. a 16 bit Hardware Model.

The ability to plug into a std 8051 socket and execute std 8051 binaries and then provide additional functionality has caused all of the manufacturers to make hard decisions about how to achieve this extra functionality.

I remember talking to DALLAS when they were designing the '320 series ( a rep gave me the number i have no special pipe) and they were adamant about not exploiting the A5H unused opcode to expand the instruction set and prefered to use SFR's to implement additional functionality. So now you use an SFR to switch data pointers, designate a DEC DPTR functionality, etc.

Now intel chose to implement additional features using the A5H opcode as a code prefix. This allowed (in non page mode) a user to plug the chip into an existing socket and incrementally implement the expanded instruction (such as "Add DWord, DWord" or "MUL WReg,WReg".

Philips prefered a clean approach to a microcontroller and to deal with legacy issues with a well defined and supported upgrade path.

Now if i need write to 16 bit periph's i need a processor with this width of data bus and '51 variants don't do this but '51 "influenced" processors do.

Good issue.

regards,
p