The 8051 is microcoded so it doesn't quite fit the RISC Model (unless you are using the FHG8051 Microcontroller or another VHDL '51).

RISCs were heralded (by IBM) as optimized for the most common operations extant in code analyzed at the time.

Their goal was;

The optimization of those instructions which execute most frequently.

Load and Store instructions, which if memory serves, comprised 40% of operations within the large code set analyzed (state trace not lexical frequency of occurance).

This optimization was achieved through hard-wired instruction logic instead of the microcoded instruction decoder architecture common then (and now)

If the resulting instruction set was kept small, production yields would be better due to a less complicated chip architecture.

The processor would also execute (on an instruction by instruction basis) faster than it's comparable geometry/clock rate CISC cousin.

The implementation of Large Register sets were to allow operations at core speed with the result "burst" into global memory at the slower bus interface rate.

Also a 1 clock per instruction execution rate per commonly used instructions was a goal (long since achieved). 1 clock per instruction is typical of most DSP, RISC processors.

The '51 does have a 1 clock per instruction offering in the ds89C420 which implements many 1 clock per instruction opcodes and as a result is very fast.

Multiple Parallel Execution Unit's and speculative execution have provided CISC with lot's of power and the CISC vs. RISC debate is now so obscure as to be almost purely conceptual, not practical, as CISC implement lot's of hardwire logic.

regards,
p