Frankly Seamus, its what we would call "a right bag of spanners" Can YOU describe what you think it does ?

I certainly wouldn't do display functions in the ISR for a start - keep them until an answer is ready:display the answer while the isr waits for the next one. The timers can be started and stopped by the signal you are trying to process, with no, or little, code overhead.

What are you proposing for your FPGA idea ? Once you get to grips with the ADUC it might do all you want.

Steve