I have just written this vhdl implementation,it uses three nor gates
direction is an output which is high for one direction low for the other,Nclk is a negative going clk output to drive your counter.
Its very basic,uses generic library and is just written very quickly to show how to implement the idea in a small pld.

library ieee;
use library.std_logic_1164.all;

entity decode is
port(a,b : in std_logic;

Nclk:out std_logic;
direction:out std_logic);
end decode;

use ieee std_logic.all;
entity nor is
port(a,b:in std_logic;
Q:out std_logic);
end nor;

architecture behavior of nor is
begin
Q<=not( a or b);
end behaviour;

architecture structural of decode is
component nor
port(a,b: in std_logic;
Q:out std_logic);
end component;
begin
signal Aprime: std_logic;
signal Bprime: std_logic;
direction<=Bprime;
gate0: nor port map(a=>a,b=>Bprime,Q=>Aprime);

gate1: nor port map(a=>b,b=>Aprime,Q=>Bprime);

gate2: nor port map(a=>Aprime,b=>Bprime,Q=>Nclk);

end structural;