I have used CPLDs for so long that I have forgot the 74... numbers, but here it is

If you are using multiple latches:
use an 8 input nand and another gate to decode addresses 0xfffx
use another decoder to decode as much of the last hex digit as you need, this one enabled by the output of the first decoder.

If you are using only one latch:
use a decoder circuit (ands/nands) to isolate addresses 0xffff

The output of the first/only decoder is used to enable/disable chip select of your RAM.

The output of the second/only decoder is used to enable read((OE)if input)/write((clk)if output) of your latch(es).

You then "talk" to your I/O as if it was memory at the selected addresses.

An output latch can be basically any latch, an input latch (which in some case is not a latch but a gate) need be tri-state output

Erik