Erik, Steve:

Paul told us that the lines in question are the AD0-AD8 lines. (Although I think he meant AD7). This is the combo address / data lines of the generic 8051. These lines DO operate in 3 state mode. In particular the processor goes input mode during a read cycle and the RD/ line will take the properly addressed ROM/EPROM/FLASH/RAM/PERIPHERAL chip out of tristate and into active drive mode and then back to tristate at the end of the RD/ pulse. A similar thing will be happening when the PSEN/ line accesses external code memory.

So my use of 3-state was applicable.

Michael Karas