Michael,

I don't know the equations for a boost supply off the top of my head, but looking at the circuit topology it seems to me that if the output current increases, the N-FET is required to be on a longer percentage of the sample period (that is, it's duty cycle increases).

Here's a couple of observations -

(1) If you need to decrease the output ripple, you can increase your sample rate or decrease the output filter frequency -
1/[2*pi*sqrt(LC)]. If the sample rate is increased, the loop has the potential for a faster settling time - if compensated properly.

(2) Some means of adjusting the loop to account for varying load current is needed - such as a PID or lead-lag network. I've been using some buck converters lately and find in the app notes that a series resistor and cap from the error amp output to ground is used as compensation. It acts like an analog PID. If you choose to implement a PID, rather than coding as a P.I.D. explicitly, why not write the analog transfer function for the PID, then convert it to the discrete time domain using a tranform such as s = [1-z^(-1)]/T (Rectangular method) or use the Trapezoidal method - don't forget to include the gains of each term Kp, Ki and Kd. If you're constrained for processor time and have to operate at a less than desirable sample rate use the Trapezoidal method as it has less frequency "warping" than the Rectangular method.

(3) Finally, if there is the potential for saturating the inductor, consider adding a method to sense inductor current and letting the processor know so the program logic knows when to back off and protect the hardware.

Looks like fun,

Bruce