Actually, it is TI's 16c750 in polling 450 mode. I'm fightening with this part the whole day. The state of status register after reset is 0x60, that is Transmitter Holding Register (THR) and Transmitter Empty (TEMT) bits are set. After I send a byte, the status returns to its normal state after several hundred cycles (CPU running at 48MHz). If I read status immediately after write transaction the status returns zero value forever. As a result, I can't determine the moment when the started serial transfer is complete (THR = 1) to write next byte.
When I reduce the number of delay cycles between write transaction and status request to a hundred machine cycles the status stalls in TEMT bit set state. This means that byte is moved from THR to TSR and can't be shifted out.
Here is my code:

	// DATA is open-collector 8bit data bus
	// P1 serves as address selector for UART's registers, /ADS is always low

	// set divisor = 48, that is 9600 baud with 7.372.800 Hz cystall
	// seems this section does not cause any problems
	UART_CS = 0;
	P1 = (P1 & ~UART_ADR_MASK) | UART_LCR;
	DATA = 0x80; //prepare for DLSB setup
	nWR = 0;
	nWR = 1;
	P1 = (P1 & ~UART_ADR_MASK) | UART_RBR_THR_DLL;
	DATA = 48; 
	nWR = 0;
	nWR = 1;
	DATA = 3; // 1 stop bit, no parity, reset DLAB to 0
	P1 = (P1 & ~UART_ADR_MASK) | UART_LCR;
	nWR = 0;
	nWR = 1;

	// write a byte to Tx, this causes problems
	DATA = 'A';
	P1 = (P1 & ~UART_ADR_MASK) | UART_RBR_THR_DLL;
	nWR = 0;
	nWR = 1;
	for (temp2 = 0; temp2 < 1; temp2++) // there are problems if these ...
		for (temp1 = 0; temp1 < 100; temp1++); // ... do-nothing loops are not included


	DATA = 0xFF; // disconnect bus from ground allowing UART assert a value to it
	P1 = (P1 & ~UART_ADR_MASK) | UART_LSR; // select address of status register
	nRD = 0;	// put contents of addressed register on the bus
	for(;;)	{			/*start of endless loop*/
		send_byte(DATA); // def = 60
		delay_msec(1000);	/*wait about a second*/
	}

I'll be wery happy if anybody dealt with these parts. Should I de-activete /CS signal after each read/write transaction? Can I read registers switching only adresses without touching activated /RD line? May be there is a tutorial on this part. TI's spec. is very stingy, as usually. Thanks.