Steve:
You need to read my reply to you on the other thread. You are wasting your time thinking about how "simple" this will be. It is not simple.

First off you cannot simply modulate the write data line to the disk drive with any old pulse width you desire. The reason for this is as follows:

When you modulate the write data line the transitions of the signal cause the flux of the magnetic medium on the diskette to reverse polarity. To the end of working the write side this would be fine. The problem comes in on the read side. When a head detects a flux reversal on the diskette you get a pulse out of the head that is either positive or negative based upon the direction of the flus reversal. There is a circuit in the chip on the floppy drive that has basically a couple of one-shots and a set of flipflops that try to "recover" a waveform that looks like that originally written. These one shots are designed with a R/C time constant that is matches to the nominal data rate expected for the type of drive in question. If the data rate written originally is out of range the oneshots and flipflops on the drive do not work correctly.

It is very necessary that the data recovery process from a floppy disk use a PLL so that the clocking of the data can be recovered from the data transitions. Data recovery is complex and is made so becasue the motor driven diskette has lots of ISV (instantaneous speed variations) and adjacent magnetic domainf recorded onto the diskette have a tendancy to effect each other and move the apparent edges where the original bit cells were written.

It is also necessary for the pulse stream used to record to and recover from a floppy disk to be designed so that it can work properly no matter what the polarity of the detected flux reversals is. Most often the protocol used is a 1F/2F frequency system so it us frequency and not pulse phase that represents 1's and 0's on the media.

When you design a diskette controller even the likes of the older NEC type uPD765 chip will require an external PLL and data recovery circuit at the data rates that the current day 3.5 inch floppy drives are designed for. Thus when you look for a chip you should look for the more modern types that have a decent PLL built on board the chips. And I can tell you from experience that there were plenty of controller chips sold in the market place over the years that proported to have on-board data recovery that turned out to be outright crap.

The simplest floppy disk controller of all time that I have seen, that proved to be reasonably reliable, was the one that Steve Jobs designed into the Apple II computer. It took a few chips and a couple of PALs plus an intensive piece of 6502 code to operate the diskettes. At one time in the '80s I actually wired up an Apple II controller on to a S100 board as a piggyback and interfaced it to a Z80 as a means of providing a way to be able to read and write Apple II diskettes at the file level under the CP/M operating system. It is extremely doubtful to me however that a modern day 3.5 inch drive would work with an Apple II controller becasue of the fact that the core data rate is 4x faster on a 1.44 MB floppy drive than on the original Apple II Micropolis 5.25 inch drives. (Please don't ask for any schematic drawings and software listings of that work I did.....it is long gone from my archives).

I really really think you should back off this floppy disk thing and consider the interface of a Compact FLASH card to your processor. At the basic level these cards can work as a sector oriented device with 512 byte blocks that are accessible in a random access manner. You can interface to a CF card with an 8-bit interface via a map of 8 I/O ports. (You can memory map the ports too if you wish). CF cards also support 16-bit transfers for data too but this is not necessary. The cards have onboard sector buffers so it is simple to read/write the FLASH and then transfer data at the leisure speed your processor supports to/from this sector buffer. You should be able to interface a CF socket to the Z-80 with a small CPLD or a I/O decoder circuit and a couple of 8 bit wide buffer chips (an HC245 type thing for the data lines and a HC244 type thing for the minimum required address lines and CS/,WR/,and OE/ control lines.

There are even some simple schematics at the Sandisk web site.

Michael Karas