I think that bit addressable could also mean a peripheral in an external memory mapped device, such as a CPLD, whereby a single I/O can set or clear the bit. For example, one could make a CPLD that decoded the external memory address 0FFF5h and 0FFF6h. The CPLD could support setting or resetting up to 128 bits using a format of data being sent to 0FFF5h as follows:

  D7    D6    D5    D4    D3    D2    D1    D0
+-----+-----+-----+-----+-----+-----+-----+-----+
| 0/1 |                                         |
| Bit |   Bit Address to select 1 out of 128    |
|State|                                         |
+-----+-----+-----+-----+-----+-----+-----+-----+

Setting a bit would use code as:

    MOV   DPTR, #0FFF5h
    MOV   A, #Bit_Number+08h  ;to set the bit
    MOVX  @DPTR,A

Clearing a bit would be done in similar manner:

    MOV   DPTR, #0FFF5h
    MOV   A, #Bit_Number+00h  ;to clear the bit
    MOVX  @DPTR,A

The CPLD would also accept the bit selection pattern in the data sent to 0FFF6h to select the current state of a bit. The data format sent out would be:

  D7    D6    D5    D4    D3    D2    D1    D0
+-----+-----+-----+-----+-----+-----+-----+-----+
|     |                                         |
| N/A |   Bit Address to select 1 out of 128    |
|     |                                         |
+-----+-----+-----+-----+-----+-----+-----+-----+

Then upon a read at 0FFF6h the returned data would be:

  D7    D6    D5    D4    D3    D2    D1    D0
+-----+-----+-----+-----+-----+-----+-----+-----+
|Curr |                                         |
| 0/1 |     Not used. Read back all zeros.      |
|State|                                         |
+-----+-----+-----+-----+-----+-----+-----+-----+

The code to read the state of a bit using this scheme could look like:

    MOV   DPTR, #0FFF6h
    MOV   A, #Bit_Number    ;Bit number 0 -> 127
    MOVX  @DPTR,A           ;Select the bit number
    MOVX  A,@DPTR           ;Read current bit state

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This scheme can alternately be made to work by attaching the CPLD to a set of port pins instead of the external memory bus. For example the CPLD could be connected to P1.0 -> P1.7 and to P2.0 and P2.1. Define the eight port 1 bits in a format similar to the example above. P2.0 would serve as the bit setting strobe in the CPLD and P2.1 would be the bit reading strobe.

Code as follows could then be used to send the Carry flag bit state to any of 128 output bits.

    MOV   P1,#Bit_Number     ;select the desired bit
    MOV   P1.7,C             ;copy carry to output bit
    SETB  P2.0               ;strobe the bit into CPLD
    CLR   P2.0

Similarly the current state any of 128 bits could be read into the Carry flag with code as follows:

    MOV   P1,#Bit_Number+080h ;select bit & make sure
                             ;P1.7 is an input
    SETB  P2.1               ;enable read @ CPLD
    MOV   C,P1.7             ;copy the bit to carry
    CLR   P2.1

With the selection of the appropriate CPLD the up to 128 actual bit I/Os could be implemented as either OUTPUT only bits, OUTPUT with READBACK or INPUT ONLY. Alternatively the pins could be configured like the 8051 pins in a quasi-bidirectional mode so that an OUTPUT to the bit can set it high or low and a read at the same bit number would return the current state of the pin.

Michael Karas