James:
Your choice really has to be made by looking VERY closely at how that 2K SRAM of the existing 6502 is used. If it holds a lot of data in the likes of arrays, tables, data structures, linked lists or just even 100s of global variables that are closely coupled as the data sources and destinations of various software algorithms in the code, THEN maybe an 8051 type processor is not the best choice unless you use something like a processor that can execute the following type of 8051 instructions:

    MOV DPTR, #Abs16,  (3 bytes - 2 cycles)    
    MOVX A, @DPTR      (1 bytes - 2 cycles)
                       (On 12 MHz std 8051 this is 4 uSec)

... in the same time it takes the 6502 to run this type of instruction:
Save This Code
    LDA  Abs16Addr     (3 bytes - 4 cycles) 
                       (at 2 MHz this is 4*500nSec

You can get this kind of preformance if you use a derivative at 6 clock divider running at 12 MHz.
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Also keep in mind that if the existing code makes frequent references to the SRAM at locatons beyond the "zero page" with instructions using the... 

Abs16Addr,X
Abs16Addr,Y

...addressing modes where both X and Y indexing are used in the same loops or algorithm, then I would look carefully at derivative 8051 type parts that have dual data pointer.
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Most other instruction translations from 6502 to 8051 should convert with almost equivalent performance. 

Michael Karas